Plenary Talk

K - AI Semiconductor; Present and Future

Abstract

As AI continues to push the boundaries of computing, Korea’s semiconductor ecosystem is rapidly advancing to meet the demands of next-generation AI applications. This talk will highlight recent progress in processing-in-memory, neuromorphic computing, and energy-efficient AI accelerators, with innovations that span from circuit-level design to full-stack system integration. These advances are being driven by a new wave of startups, such as Rebellions, HyperAccel, Mobilint, UX Factory, and OnNeuroAI, alongside collaborations with industry leaders such as Samsung and SK Hynix. By bridging foundational R&D with large-scale commercialization, Korea’s AI semiconductor efforts offer a compelling model of innovation-from silicon ideation to deployment. The talk will conclude with strategic insights into Korea’s global positioning in the silicon race and the role of integrated research ecosystems in shaping the future of AI hardware.

Biography

Hoi-Jun Yoo is a member of National Academy of Science of Korea, the KAIST ICT Endowed Chair Professor of School of Electrical Engineering and Dean of the AI Semiconductor Graduate School at KAIST. He is also the Director of the AI-PIM Research Center, and the Director of KAIST Institute of IT-AI Convergence. His research focuses on Wearable Healthcare systems, AI-SoC design, High-Speed and Low-Power memory architectures, and PIM circuits. He has published over 200 journal papers and more than 400 conference papers in these areas. Prior to joining KAIST in 1998, he worked for Bell Communications Research developing VCSELs. He is a Fellow of IEEE, has served as an AdCom member of the IEEE SSCS since 2022, the TPC Chair of ISSCC, and the Chairman of the Steering Committee of the A-SSCC. 

Prof. Yoo has been at the forefront of semiconductor and system design innovation, with his group’s research on physical-AI accelerators integrated into mobile XR/Robotic SoCs. His achievements have been recognized with numerous awards, including the Kyung Ahm Scholarship Award, the KAIST Grand Prize for Academic Excellence, multiple IEEE Best Paper Awards, and Top 5 Paper Contributor in 70 years of ISSCC, and Top 10 Paper Contributor in 60 years of ISSCC.

Revolutionizing Long-term Memory for AI with High-Capacity and High-Speed Storage

Abstract

Memory systems are becoming essential for LLM/VLM-based AI agents and robots, enabling them to behave more intelligently and autonomously based on past experiences and knowledge. Such memory systems are expected to play a role beyond merely serving as an information pool; they must also be capable of selecting and retrieving relevant information based on the current context and processing it in a way that LLMs/VLMs can effectively utilize. In this plenary talk, we will introduce the foundations of memory systems designed to efficiently handle the ever-growing long-term memory for AI agents and robots, with a particular focus on high-capacity and high-speed storage and emerging memories, as well as the associated device and process technologies and information retrieval techniques. We will also discuss future prospects in this area.

Biography

Hideshi Miyajima, Ph.D. at KIOXIA Corporation (born 5 March 1964), has been at the forefront of leading the development of their cutting-edge 3D Flash Memory (BiCS FLASHTM) technology since 2012. He earned his BS/MS degrees from Tokyo Institute of Technology in 1987/89, followed by a Ph.D. from Nagoya University in 2019. His journey began at TOSHIBA Corporation in 1989 as an R&D process engineer. TOSHIBA's memory division was spun off as KIOXIA Corporation in 2017. Throughout his career, Miyajima has been dedicated to advancing Cu/low-k interconnect technologies for logic devices. Currently, he continues to demonstrate strong leadership in the development of cutting-edge 3D NAND processes, playing a crucial role in both research and manufacturing efforts.

I don’t vibe, I code: AI-Assisted Agile Chip Design

Abstract

AI is everywhere — it writes poems, chats endlessly, and even claims it can design chips. But let’s be honest: AI is not an architect. It cannot imagine a concept, invent an architecture, or weigh the delicate trade-offs of PPA. That vision belongs to the engineer — the great engineer.

What AI can do is execute — fast and not always precisely. But if we only “vibe” with AI through natural language, the results are vague and easily misinterpreted. In chip design, precision is non-negotiable. That’s why we code. Just as software advanced from assembly to C, Rust, and MicroPython, hardware design must move beyond Verilog toward higher-level hardware construction languages and workflows that enable agility and innovation.

This talk will introduce an AI-assisted agile design flow, showing how engineers can harness AI power with structured methods using DSPy, MCP, and agent systems. With the blueprint defined by the designer, LLMs can assist in both design and verification — from generating RTL modules and refining microarchitectures to accelerating verification and debugging. A custom SoC case study will illustrate this: a Chisel-based generator enables rapid design space exploration with PPA feedback, while LLM-driven workflows support coding and verification.

The message is clear: the future of chips will not be built by vibing with AI hype, but by those who code their insight into silicon — with AI as their fast, tireless, and occasionally overconfident collaborator.

Biography

Dr. Nick Tan has over three decades of experience at the intersection of semiconductors, systems innovation, and entrepreneurship, spanning the U.S., Europe, and China.

He earned his B.Eng. (1988) and M.Eng. (1991) in Electronics Engineering from Tsinghua University, and a Ph.D. (1994) in Electronic Systems from Linköping University, Sweden.

Dr. Tan began his career at Ericsson R&D in Sweden, pioneering communication-centric data converter architectures while teaching at Linköping University, where he was recognized as its youngest professor. He later joined GlobeSpan (Bell Labs spin-off) in New Jersey, establishing its mixed-signal division and leading DSL chipset development that made GlobeSpan the #1 DSL supplier worldwide. He went on to found AnaLutions, Inc. in California, a mixed-signal IC firm serving clients such as Texas Instruments and MediaTek, before creating Vango Technologies, Inc. in 2006, a fabless semiconductor company focused on Energy IoT and smart grid ICs. Vango grew to over $100M revenue and was acquired by Beijing SmartChip in 2019, one of China’s top three fabless companies. Dr. Tan now serves as its Chief Scientist. Alongside his entrepreneurial work, he is a Professor at Zhejiang University’s College of Integrated Circuits, mentoring students recognized with national chip innovation and outstanding Ph.D. thesis awards. He holds 33 U.S. patents and numerous Chinese patents and has authored three books and 100+ papers. Today, Dr. Tan drives innovation at the convergence of AI and chip design, bridging academic research and industrial practice to shape the future of chip design.

Transceivers in Recent Commercial Wireless Communication Devices

Abstract

This paper will first introduce wireless communication nonidealities, transceiver design challenges, then present state-of-the-art WiFi and 5G FR1/FR2 transceivers. Considerations for transceiver process selection and chip partition will be addressed. Snapshot of latest 3GPP and WiFi8/9 progress in standard meetings will be covered in the last part of the talk.

Biography:

1999 – 2001: Optical storage RTL designer, MediaTek Inc, Hsinchu, Taiwan.

2004 – 2006: Senior design engineer, Communication Research Lab, Intel, Hillsboro, Oregon, USA.

2006 – now: RF design, MediaTek Inc, Hsinchu, Taiwan.

2011 – 2014; 2019 – 2023: IEEE ISSCC TPC

Education:

EE BS 1996, National Tsing Hua University, Hsinchu, Taiwan.

EE MS 1997, National Tsing Hua University, Hsinchu, Taiwan.

EECS PhD 2004, Cornell University, Ithaca, NY, USA.