Why Robots Need Your Chips: Opportunities for ASIC and FPGA in Robotics

Abstract

Artificial Intelligence has long advanced by imitating human intelligence: first in vision, then in language. The next frontier is the imitation of human actions, where robots learn from demonstrations to grasp, walk, and manipulate objects in the physical world. This shift introduces unprecedented hardware challenges: high dimensional control of dozens of joints, strict millisecond feedback, and continuous adaptation to uncertain environments. This talk describes robotic imitation learning in terms of a three layers architecture: Action planning with large models such as LLMs, Motion generation with sequence models producing trajectories, and Motor control with predictive and feedback controllers. Each layer exposes distinct bottlenecks that cannot be solved by CPUs or GPUs alone. ASICs and FPGAs can provide low precision computing, reconfigurability, parallel sampling, and near sensor processing, enabling robots to operate in real time with sustainable energy budgets. By tracing the evolution of robots from early industrial arms with 6 degrees of freedom to modern humanoids with over 50 degrees of freedom, the talk highlights why real time hardware acceleration is no longer optional. These trends make robotics an emerging application for chip designers, one that requires sustainable advances in circuits and systems and promises opportunities for lasting contributions.

Biography

Hiromitsu Awano received the B.E. degree in computer science from Kyoto University, Kyoto, Japan, in 2010, and the M.I. and Ph.D. degrees in informatics from Kyoto University, in 2012 and 2016, respectively. From 2013 to 2016, he was a Research Fellow of the Japan Society for the Promotion of Science (JSPS, DC1). In 2016, he joined Hitachi, Ltd., Research and Development Group. From 2017 to 2018, he was an Assistant Professor with the VLSI Design and Education Center (VDEC), the University of Tokyo. From 2019 to 2020, he was an Associate Professor with the Graduate School of Information Science and Technology, Osaka University. Since 2020, he has been an Associate Professor with the Graduate School of Informatics, Kyoto University. His current research interests include integrated circuit design for AI hardware, reconfigurable computing, computing-in-memory, and robotics applications. He has been a member of the FPGA Subcommittee of A-SSCC since 2019. He has served on the technical program committees of major conferences including DAC, ICCAD, DATE, and ASP-DAC, and he served as Track Chair of AI2. AI/ML Application and Infrastructure for DAC 2025.

From Silicon to Intelligence: Redefining System Design in the Era of AI Semiconductors

Abstract

As artificial intelligence evolves from model-centric development to become core infrastructure, cognition through computation is being realized in silicon. This talk will examine how AI semiconductors are impacting the entire spectrum of system design—from individual processor cores to large-scale computing ecosystems.

We will explore how the co-design of hardware, software, and data is driving the future of computing, while also highlighting the emerging challenges in power, scalability, and memory. The discussion will focus on a path toward energy-efficient, resilient, and human-centered AI systems. Ultimately, this talk aims to show that the true AI revolution lies not in bigger models, but in 'smarter systems,' engineered all the way from silicon to intelligence.

Biography

Soojung Ryu has built her career at the intersection of processor architecture and AI semiconductor development, holding leadership roles in both academia and industry. She is currently a visiting professor at Seoul National University, where she is engaged in research on heterogeneous AI computing systems — focusing on benchmarking frameworks, performance evaluation tools, and ecosystem development for scalable and efficient AI deployment. Previously, she served as the CEO of SAPEON Korea and SAPEON Inc. (US), where she led the development and commercialization of Korea’s first low-power AI accelerator chip for servers. Prior to that, she spent 14 years at Samsung Electronics (Advanced Institute of Technology and S.LSI), where she contributed to DSP and GPU processor architecture as a Research Master and Vice President.

Future Computing Paradigms for Embodied AI

Abstract

Professor Ningyi Xu has long been engaged in research on domain-specific architectures (DSA), reconfigurable computing, software and hardware systems for AI chips, and heterogeneous computing. He has led pioneering research and practical work in computing fields such as "large-scale data centers" and "machine learning & deep learning". During his tenure at Microsoft Research Asia, he led the development of a custom acceleration system for Microsoft data centers, which marked the world’s first large-scale application of FPGAs in data centers. At Baidu, he contributed to the Kunlun Chip project—over 20,000 units of this chip were mass-produced, enabling partial replacement of GPUs. As artificial intelligence enters the era of large models, Professor Xu has carried out systematic work on large-model computing power at the Qingyuan Research Institute of Shanghai Jiao Tong University. He conducts research on innovative large-scale chips at the Large Chip Center of Pujiang Laboratory. He also incubated Huixi Technology, a high-tech enterprise focusing on embodied intelligence and in-vehicle intelligent computing chip design, which addresses the demand for high-computing-power AI chips in intelligent robots and autonomous driving.

Biography

Ningyi Xu is a tenured full professor at the School of Computer Science, Shanghai Jiao Tong University. He is also the founder of Huixi Technology. He holds a Bachelor’s degree, a Master’s degree, and a Doctoral degree from Tsinghua University. His research interests include domain-specific computing, computer architecture, parallel computing, and machine learning systems. Previously, he served as a Researcher and Head of the Hardware Computing Group at Microsoft Research Asia, and Chief Architect at Baidu’s Intelligent Chip Division.

Participate in panel discussion

Biography

Prof. Hao Yu received his B.S. degree from Fudan University and Ph.D. in Electrical Engineering from UCLA. He is the Founding Associate Dean at School of Microelectronics, Southern University of Science and Technology (SUSTech) in Shenzhen. Prior to joining SUSTech, he was a faculty of Nanyang Technological University (NTU), Singapore.  His current research interest includes 3DIC and embodied AI chip design with a number of startups for commercialization.