Datacenter Interconnect standard development and thinking 

Abstract

The exponential growth of artificial intelligence (AI) workloads, particularly in large-scale GPU clusters for distributed training and inference, is driving fundamental innovations in chiplet interconnect standards and optical integration strategies within system-on-chip (SoC) architectures. This presentation analyze the reason and necessity of standard effort in data center SoC such as CPU/GPU/Switch, summary the standard development of three critical advancements reshaping data center SoC design include (1)chiplet interconnect, (2)co-packaged optical (CPO) interconnects, (3)scale-up interconnect between GPUs, finally conclude with some insights into the standardization challenges including technology and interoperability across multi-vendor ecosystems.

Biography

Qinfen Hao obtained his Ph.D. in System Architecture from the Institute of Computing Technology, Chinese Academy of Sciences in 2001. He is currently a Professor at the University of the Chinese Academy of Sciences (CAS) and the Director of the Interconnect Technology Laboratory of the Institute of Computing Technology, CAS. He has pioneered the first teraflops high-performance computers, the first 32-WAY high-end SMP servers, the first cache coherence interconnect chips in SMP server, the first ARM processor in China. He published more than 50 research papers with more 100 granted patents. He has won the second prize of the Chinese National Science and Technology Progress Award twice. He served as General Chair for China Interconnect Technology and Industry Conference, and China Chiplet Developers Conference. He is leading the Chiplet Interface Circuit Standard Development in China and also Chairing the IEEE P3468 Chiplet Interface Circuit Standard Working Group.

The Challenge to Real-time Demodulation and Decoding of QAM Signals using Optical SVM Classifiers

Abstract

 Multilevel modulation formats such as Quadrature Amplitude Modulation (QAM) are widely used in modern wideband communications. QAM waveforms are distorted by various influences during communication. In this talk, we introduce a method to correctly receive the distorted 16-QAM waveform using a Support Vector Machine (SVM) classifier that identifies the received 16-QAM code based on a pre-learned distortion tendency. SVM is one of the most studied supervised ML models. It is a two-class classification method based on the max-margin algorithm that maximizes the margin of the two classes in the training dataset. This two-class classification can be achieved by performing multiply-and-accumulate (MAC) operations. We first present a digital CMOS implementation of the SVM classifier. Digital MAC operation is used for each classification task in this digital CMOS SVM classifier. We then introduce our challenge to extend it to an optical implementation. It uses optical modulators for analog multiplication and multi-input photodetectors for analog addition for performing optical MAC operation. We also showcase our originally developed electro-optical mixed signal simulation model that can be handled by SystemVerilog, Verilog-AMS, and SPICE co-simulation framework. This model takes the physical properties of optical modulators into account that perform multiplication operation in the optically implemented SVM classifiers. It also allows the inference accuracy evaluation of the optical SVM classifier with a large number of input communication symbols. Finally, we will discuss the future potential of the optical SVM classifier.

Biography

Prof. Tohru Ishihara received his Ph.D. degree from Kyushu University in 2000. He served as a research fellow of the Japan Society for the Promotion of Science (JSPS) from 1997 to 2000. After working as a research associate at the University of Tokyo and as a research staff at Fujitsu Laboratories of America, he became an associate professor at the System LSI Research Center, Kyushu University in 2005. In 2011, he joined the Graduate School of Informatics at Kyoto University as an associate professor. Since 2018, he has been a professor at the Graduate School of Informatics, Nagoya University.

He has authored and co-authored numerous papers in international journals and conferences and contributed to the advancement of energy-efficient computing, low-power digital design, and novel computing architectures, including optical and memory-centric computing. His recent research focuses on ultra-low-power design using emerging memory technologies and optical circuits. Prof. Ishihara is a member of IEEE, IEICE, IPSJ, and ACM. He has also served on the program committees of major conferences, including ASP-DAC, ISLPED, and DATE.

Activating Glass Substrates: A New Approach to Next-Generation Advanced Packaging

Abstract

This talk presents a forward-looking perspective on the evolving role of glass substrates in next-generation semiconductor packaging. Traditionally viewed as passive interconnect carriers, glass substrates are now emerging as active participants in system-level performance. With their low-loss dielectric behavior, excellent electrical insulation, dimensional stability, and atomically smooth surfaces, glass substrates contribute not only to superior signal integrity and thermal management but also to the functional expansion of the packaging platform. Recent advances in the integration of atomically thin semiconductors—such as carbon nanotubes (CNTs), two-dimensional (2D) materials, and oxide semiconductors—have begun to blur the boundary between chip and package. CNT/2D CFETs are showing strong promise for future logic nodes beyond silicon, while oxide semiconductors like IGZO are enabling high-density, capacitorless DRAM. Importantly, these materials can now be deposited or grown directly on amorphous glass surfaces at low temperatures, allowing for the implementation of logic, memory, and even RF circuit elements on the substrate itself. This talk will explore how glass substrates, once passive, are being redefined as signal-intelligent platforms. By hosting both high-speed signal paths and device-level functions, glass is poised to play a central and active role in the future of chiplet-based microelectronic systems.

Biography

Jimin Kwon is an assistant professor in the Department of Electrical Engineering at Ulsan National Institute of Science and Technology (UNIST). He earned his MS and PhD degrees from Pohang University of Science and Technology (POSTECH), focusing on RF/analog CMOS IC design and TFT circuits, respectively. Previously, he conducted postdoctoral research at Stanford University, exploring advanced upper-layer logic and memory devices utilizing carbon nanotubes and oxide semiconductor materials for monolithic 3D (M3D) integration. His current research focuses on emerging heterogeneous integration technologies, i.e., M3D ICs and advanced packaging technologies.