Tutorials

Noise-Shaping SAR ADC: Design, Development, and Deployment

Abstract

The Noise-Shaping (NS) SAR ADC is a compelling architecture that has gained significant attention over the past decade. By combining the energy efficiency and simplicity of the SAR ADC with the noise shaping capabilities of Σ-Δ ADC, the NS SAR architecture offers an efficient and cost-effective solution that scales well with advanced CMOS technologies. This tutorial provides an overview of the NS SAR ADC, covering the fundamental operating principles, key design considerations, and inherent challenges of the architecture. The tutorial then explores recent advancements, including innovations in loop filter design, techniques for DAC mismatch and kT/C noise mitigation, and methods for bandwidth enhancement. A review of state-of-the-art works will also be presented, highlighting performance trends and architectural evolution. Finally, the tutorial discusses the practical applications of NS SAR ADCs, with particular emphasis on their growing role in hybrid ADC architectures.

Biography

Lu Jie received the B.Eng. degree from Zhejiang University, China, in 2017, and the Ph.D. degree from the University of Michigan, USA, in 2021. Since 2022, he has been with Tsinghua University, China, as an Assistant Professor. His main research interests include mixed-signal integrated circuit design, hybrid-architecture ADCs, reconfigurable mixed-signal circuits, and mixed-signal computation. Lu Jie currently serves as the Technical Program Committee (TPC) member for A-SSCC and CICC.

Computing-in-Memory Processor for Large-Scale AI Models

Abstract

With the rapid development of large-scale AI models, AI computing has entered a new era. The massive parameter scale and multimodal learning capabilities of large models enable them to handle more complex and general-purpose intelligent tasks, while also raising tremendous demand for high-performance AI processors. However, the frequent and extensive data movement severely restricts the AI processor performance due to the von Neumann bottleneck. Computing-in-memory (CIM) architecture, which deeply integrates compute and memory, offers a promising solution to break through this limitation and achieve a balance between high performance and energy efficiency. However, in the large-scale AI model era, CIM processors face new challenges such as mixed-precision computing, sparsity processing, massive parameter storage, and inter-chip communication. This tutorial will discuss how to design CIM processors with multi-level architecture innovations to tackle these challenges and provide high-performance and efficient support for the large-scale AI model deployment.

Biography

Fengbin Tu is an Assistant Professor and the Associate Director of the Institute of Integrated Circuits and Systems at The Hong Kong University of Science and Technology, NSFC Excellent Young Scientist, and a core faculty member of the AI Chip Center for Emerging Smart Systems (ACCESS). He received the Ph.D. degree from the Institute of Microelectronics, Tsinghua University, in 2019, with the Tsinghua Excellent Dissertation Award. His research interests include AI chip and computing-in-memory. His AI chips Thinker and ReDCIM won the 2017 ISLPED Design Contest Award and 2023 Top-10 Research Advances in China Semiconductors. He received the 2024 WAIC Yunfan Award-“Bright Stars”. He has published two books, Artificial Intelligence Chip Design in 2020, and Architecture Design and Memory Optimization for Neural Network Accelerators in 2022. Dr. Tu’s research has been published at top conferences and journals on integrated circuits and computer architecture, including ISSCC, JSSC, DAC, ISCA, and MICRO.

CMOS Time-of-Flight Sensors

Abstract

This tutorial provides an in-depth exploration of CMOS Time-of-Flight (ToF) sensors, focusing on both indirect and direct ToF methodologies. These sensors are pivotal in a range of applications, including autonomous systems, augmented reality (AR), and virtual reality (VR), where accurate depth perception is crucial. The tutorial will begin with an introduction to the basic operating principles of indirect ToF (iToF) and direct ToF (dToF) techniques, highlighting their respective advantages and challenges. We will then delve into the architecture and design considerations for each approach, from device to system perspectives. Finally, the session will examine state-of-the-art approaches, followed by a comparison of both technologies to offer valuable insights into future directions and the potential of CMOS ToF sensors in emerging technological landscapes.

Biography

Seong-Jin Kim received his Ph.D. degree in electrical engineering from KAIST, Daejeon, Korea, in 2008. From 2008 to 2012, he served as a Research Staff Member at the Samsung Advanced Institute of Technology in Yongin, Korea. From 2012 to 2015, he was with the Institute of Microelectronics, A*STAR, Singapore. From 2015 to 2024, he was an Associate Professor at the UNIST, Ulsan, Korea. In 2024, he joined Sogang University, Seoul, Korea, as an Associate Professor. His research interests include high-performance imaging devices, LiDAR systems, and biomedical interface circuits and systems. Dr. Kim has authored and co-authored 80+ peer-reviewed journal and conference papers. He has served on the Technical Program Committees for ISSCC from 2019 to 2024.

Harmonic-Mixer-Based Fractional-N Phase-Locked Loops

Abstract

Frequency synthesizers are an integral part of various applications, such as wireless and wireline communication systems. The generation of frequency sources with low phase noise under limited power, area, and many other factors has been an ongoing challenge over the years. Especially for the fractional-N phase-locked loops (PLLs), the suppression of quantization noise (Q-noise) and spurs has been one of the main challenges. Architectures based on quantization error cancellation, either in the time domain using digital-to-time converters or in the voltage domain using digital-to-analog converters, have been popular in recent years. However, the circuits used for the cancellation are often affected by PVT-related gain errors and non-linearity, requiring intensive digital calibration to prevent severe performance degradation. In this talk, we introduce some harmonic-mixer-based fractional-N PLL architectures that avoid the amplification of the Q-noise by the loop. With this concept, we can effectively suppress the contribution of the Q-noise at the PLL output without relying on intensive calibration.

Biography

Tetsuya Iizuka received the B.S., M.S., and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 2002, 2004, and 2007, respectively. From 2007 to 2009, he was with THine Electronics Inc., Tokyo, as a high-speed serial interface circuit engineer. He joined the University of Tokyo in 2009, where he is currently a Professor with the Department of Electrical Engineering and Information Systems, School of Engineering. From 2013 to 2015, he was a Visiting Scholar with the University of California at Los Angeles, Los Angeles, CA, USA. 

He was a member of the IEEE ISSCC TPC from 2013 to 2017 and a member of the IEEE CICC TPC from 2014 to 2019. He is also serving as a member of the IEEE A-SSCC and the IEEE VLSI Symposium on Circuits Technical Program Committees. From 2025, he is serving as a distinguished lecturer of the IEEE SSCS.